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CD4043BPWR
IC NOR R/S LTCH 3ST QUAD 16TSSOP
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- Fr. Teil #CD4043BPWR
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- Datenblatt CD4043BPWR DataSheet
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Spezifikationen
| Series | 4000B |
| Part Status | Active |
| Logic Type | S-R Latch |
| Circuit | 1:1 |
| Output Type | Tri-State |
| Voltage - Supply | 3V ~ 18V |
| Independent Circuits | 4 |
| Delay Time - Propagation | 50ns |
| Current - Output High, Low | 6.8mA, 6.8mA |
| Operating Temperature | -55°C ~ 125°C |
| Mounting Type | Surface Mount |
| Package / Case | 16-TSSOP (0.173", 4.40mm Width) |
| Supplier Device Package | 16-TSSOP |
| Base Product Number | CD4043 |
Übersicht
Description
Key specifications include a wide supply voltage range (typically 3V to 15V), low power consumption, and compatibility with CMOS, TTL, and other logic families due to its standard voltage levels. The device is packaged in a TSSOP (Thin Shrink Small Outline Package), with its small footprint making it ideal for compact circuit designs.
The CD4043BPWR is often used in applications requiring memory storage, signal gating, or data buffering, such as in registers, counters, or control systems. Its robustness and versatility make it a popular choice in both consumer electronics and industrial applications.
Features
1. Quad NOR Latch Configuration: Comprises four separate latches that can be individually controlled.
2. 3-State Output: Allows the outputs to be in one of three states: high, low, or high-impedance, facilitating easy interfacing with bus systems.
3. High Noise Immunity: Benefits from CMOS technology, providing good noise margin and stability.
4. Wide Supply Voltage Range: Operates between 3V to 15V, enabling usage in both low and high voltage applications.
5. Low Power Consumption: Utilizes minimal power, making it suitable for battery-operated devices.
6. TTL Compatibility: Can interface with TTL logic levels due to its wide voltage range.
7. Latch Control: Each latch has a dedicated set and reset control, enhancing functionality and flexibility.
These features make the CD4043BPWR ideal for memory storage, data buffering, and other digital logic applications.
Package
Pinout
1. VDD (Pin 16): Positive supply voltage.
2. VSS (Pin 8): Ground or negative supply voltage.
3. Individual Latch Pins (4 sets):
- Set Input (S): Activates the latch to set the output high.
- Reset Input (R): Activates the latch to reset the output low.
- Q Output: The main output, reflecting the state of the latch.
- Q̅ Output: The complementary output, which is the inverse of Q.
These latches are used in a variety of applications where memory storage or data synchronization is required. They are part of the CMOS 4000 series logic devices, noted for low power consumption and high noise immunity.
Manufacturer
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